The present application relates to semiconductor technology, and more particularly to a semiconductor structure that includes first and second semiconductor material fin stacks that are located in first and second device regions, respectively, of a semiconductor substrate and positioned between first trench isolation structures, and wherein second trench isolation structures are located at ends of the first and second semiconductor material fin stacks. A portion of the second isolation trench structure extends beneath the first and second semiconductor material fin stacks and separates the fin stacks from the underlying semiconductor substrate.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, Fin field effect transistors (FinFETs) and semiconductor nanowire transistors is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Such non-planar devices can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Bulk nanowire or FinFET isolation is not well practiced due to complications in nanowire or Fin formation. Most of the prior art proposals for forming such isolation is post fin formation or post-spacer processing. Prior art proposals for forming bulk nanowire or FinFET isolation complicate integration schemes and lead to the formation of numerous defects. As such, there is a need for providing bulk nanowire or FinFET isolation that avoids the problems mentioned above with prior art proposals of forming the same.